1. Technical Field
The present disclosure relates generally to semiconductor memory devices, and, more particularly, to an improved method and structure for forming a deep trench capacitor structure having asymmetric buried strap.
2. Description of Related Art
A dynamic random access memory (DRAM) comprises a capacitor for storing charge and a pass transistor (also called a pass gate, access transistor, or switching transistor) for transferring charge to and from the capacitor. Data (i.e. 1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. In a crosspoint DRAM memory array, bitlines and wordlines crisscross the array and a storage capacitor is accessible at every place where a bitline crosses a wordline. FIG. 1 illustrates an example of such an array in which, the wordlines cross a semiconductor surface along one axis and the bitlines cross the semiconductor surface along a perpendicular axis. A storage capacitor is formed in the bottom of each deep trench, as illustrated in the figure. An access transistor is then formed vertically along one sidewall of the deep trench above the storage capacitor, such that the gate conductor lies along that sidewall. The elements of this vertical MOSFET transistor include a drain region within the single crystal silicon at the edge of the trench, this is coincident with the “buried strap outdiffusion”, a gate conductor along one sidewall of the trench, and a source of the transistor in the surface plane under the contact to bitline (CB) areas.
In such crosspoint designs, each storage capacitor must typically be accessible from only one side of the deep trench, otherwise the one wordline, one bitline, one memory bit rule would be violated. Therefore, an interconnection is formed between the storage capacitor and the vertical sidewall only along one sidewall of the deep trench, while the deep trench is isolated along all other sidewalls. In the structure illustrated in FIG. 1, two of the deep trench sidewalls are isolated by shallow trench isolation (STI) regions. Of the two deep trench sidewalls that coincide with the active areas, a buried strap is formed along one of them, and the other sidewall is isolated.
Since the active area of the memory is defined by stripes along the-semiconductor surface, (in FIG. 1 the stripes are coincident with the bitline (BL) pattern), there needs to be methods for forming the buried strap interconnection and transistor along the one deep trench sidewall, while isolating the other sidewall coincident with the active area pattern.
Prior art methods of forming asymmetric buried strap in a trench DRAM are complicated and costly because they require either a strap mask or deposition, and etch of multiple sacrificial layers. For example, various methods include forming an asymmetric strap by adding multiple extra process steps including deposition of multiple layers including a sacrificial undoped poly layer, implanting boron into the poly layer on one side of the trench, removing the undoped poly selective to the born-doped poly, using the remaining poly as a mask to form the asymmetric strap, and finally removing the doped poly layer. However, this method is complex and it essentially increases process cost.
Accordingly, a need exists for forming trench eDRAM having asymmetric strap using alternative methods circumventing the limitations of the prior art. The present disclosure provides an improved method and structure for forming trench DRAM or embedded DRAM with asymmetric strap.